Abstract: FPGAs offer an attractive platform to build multi-ported memories. Multi-ported memories are used in modern designs on FPGAs (Field Programmable Gate Arrays). Block RAMs (BRAMs) are broadly used for multi-ported memory designs on FPGA. This paper first introduces 2R1W memory as 2R1W/4R memory; hence 4R/1W requires fewer BRAMs than 2R/1W. Compared with existing technique like Hierarchical Bank division with XOR design (HBDX) and Bank division with remap table (BDRT) with 2R1W/4R the proposed technique combines HBDX and BDRT and uses 2R1W/4R as 8R1W with 8K depth; as the memory capacity increases. For complex Multi-ported designs, the proposed BRAM approach can achieve higher clock frequencies. For 8R/1W the design requires fewer BRAMs compared with 4R/1W.

Keywords: Block RAM (BRAM), FPGA (Field Programmable Gate Arrays), Hierarchical Bank division with XOR design (HBDX) and Bank division with remap table (BDRT), Clock frequency.